The invention generally relates to electrical memory systems. In particular, the invention relates to content addressable memories.
FIG. 1 is an illustration of a content addressable memory (CAM) 10. CAM 10 has certain advantages over other types of memory, such as random access memory. Typically, other types of memory write and read data from specified memory addresses. To read data in such a system, a memory address associated with the desired data is provided and the data from that address is returned to the system.
CAM 10 determines the address associated with certain data. For example, the data having the content of xe2x80x9c00010110xe2x80x9d is stored in row address 03H (Hex) during a write operation. During a compare operation, when provided with the comparison data of xe2x80x9c00010110xe2x80x9d, the CAM 10 determines that address 03H (Hex) contains that data. Instead of outputting the data to the system, the CAM 10 outputs the address having that data content. CAMs 10 have high applicability in look-up table applications.
One CAM 10 is shown in FIG. 1. The address decoder 12 provides a row access to the content data stored in the CAM array 14. The content data location is defined by the inputs on the address line during a read operation. The content data in the CAM array 14 is sent onto the output read lines such as via the read and write circuits. The address decoder 12 also provides a row access for data to be written into a memory address for CAM array 14. To write information into the CAM array 14, the desired data from the incoming write data lines is stored into various locations of the CAM 10 based on the incoming address line information.
To perform a search of specific data within the CAM 10, the compare data lines sends the desired comparison data to the CAM array 14. If the previous data stored in any CAM location matches the incoming comparison data, a match signal is activated. A CAM encoder 16 is used to determine the address location associated with the match signal. The output circuitry 18 is used to drive out the matched row address that corresponds to the matching data location.
Additionally, some CAMs have prioritization circuitry. The prioritization circuitry is used to determine which address, based on a defined priority scheme, should be outputted if multiple match line signals are activated.
Some CAM encoders 16 use a read only memory (ROM) array. The ROM array may be programmed via mask levels prior to fabrication for use in determining the addresses associated with the match signals. A drawback to using a programmable ROM array is the extensive time and cost of developing the ROM arrays which makes them only cost effective in mass production.
Another type of CAM encoder 16, using NOR gates and combinational logic, may be implemented to encode the address information if the match signal is present. A drawback to combinational logic is that it is typically slow especially for larger CAM sizes. An alternate approach uses priority encoding schemes in tandem with combinational logic. Although these systems are typically faster than straight combinational logic, these schemes may increase the cost of the system through increased layout area, and longer testing methods.
Accordingly, it is desirable to have alternate CAM design schemes.
A content addressable memory (CAM) has a CAM array and a CAM encoder. The CAM array in response to data stored in a memory address of the CAM array matching comparison data, produces a match signal corresponding to the memory address. The CAM encoder receives the match signal and using encoded cells, produces the memory address corresponding to the match signal.